Ultra-low-power digital circuits for the Internet of Things
Tutor: Prof. Gaetano Palumbo
The work aims to the development of design techniques for integrated digital CMOS circuits (in particular flip-flops and adders) operating in near threshold.
Study cycle:
post graduate
Languages skills required:
English B1
Length:
2 months
Period:
second semester
Summer traineeships:
no
Research centre/company involved:
Lab: Microelectronic Design Laboratory http://www.dieei.unict.it/it/corsi/lm-29/aule-e-laboratori
Insurance:
Accident insurance during working hours only and Liability insurance
Benefits:
none
Traineeship type:
Erasmus traineeship